In the near future (2025-2028), the detector of the ATLAS experiment at CERN will undergo another decisive upgrade known as the Phase II upgrade. It is, therefore, necessary to redesign, using innovative technologies, not only the detectors but also the on-detector electronic systems in order to fulfill the higher accuracy, speed, and timing requirements. In the context of this Ph.D. research, the candidate will work on the design and debugging of the electronic cards for the Data Collection and Transmission (DCT) of the RPC detectors and the development of a fully automated testbench for the validation and final test of the DCT cards before their final placement on the detector.  Moreover, he will be involved in developing and optimizing prototype electronic systems to implement algorithms used for muon candidate selection and false trigger minimization. Those systems will be implemented on high performance reconfigurable digital platforms (FPGAs).